The NROM cell is a type of non-volatile memory (NVM) cell. The NROM cell is basically an n-channel MOSFET (metal-oxide-silicon, field effect transistor) device with an ONO (oxide-nitride-oxide) stack as a gate dielectric. Using nitride (silicon nitride, Si3N4) as a charge-trapping layer enables electrons (or holes) to be stored in two separate charge-storage areas, which may be referred to as two “bits”, or two “half-cells”. See, for example, Eitan et al., NROM: A Novel Localized Trapping 2-Bit Nonvolatile Memory Cell, IEEE Electron Device Lett. Vol 21, no. 11, pp 543-545 (2000), incorporated by reference in its entirety herein.
Generally, the quantity of electrons (or holes) stored in a given charge-storage area will control the threshold voltage of the half cell, and can be controlled to correspond to at least two distinct program levels. In a single-level cell (SLC) there may be two threshold voltage distributions representing, for example, binary “0” and binary “1”. In a multi-level cell (MLC), there may be four (or more) threshold voltage distributions representing, for example, binary “00”, “01”, “10” and “11”. A lowest one of the threshold voltage distributions may represent an erase state, and the other threshold voltage distributions may represent program state(s).
Programming of the NROM cell may be performed by Channel Hot Electron (CHE) injection or channel-initiated secondary electron (CHISEL) injection, to increase the threshold voltage of the half cell. Erase of the NROM cell may be performed by band-to-band Tunnel Assisted Hot Hole Injection (HHI), to reduce the threshold voltage of the half cell. Reading of the NROM cell may be performed by a reverse read method, to ascertain the threshold voltage of the half cell.
Structure of a Conventional (“Standard”) NROM Cell
FIG. 1 is a cross-sectional view, of an exemplary NROM memory cell 500 generally comprising a substrate 102, a first diffusion 104 extending into the substrate 102 from a top (as viewed) surface thereof, a second diffusion 106 extending into the substrate 102 from a top (as viewed) surface thereof, a channel 108 disposed between the first diffusion 104 and the second diffusion 106, and an ONO stack (“charge-storage stack”) 110 disposed on the top surface of the substrate 102. The ONO stack 110 comprises a first (or “bottom”) oxide layer 112, a nitride (“storage”) layer 114 disposed on the bottom oxide layer 112, and a second (or (“top”) oxide layer 116 disposed on the storage layer 114. The storage nitride layer 114 may comprise two charge storage areas (or “bits”), a right “bit” 114R adjacent the right diffusion 104, and a left “bit” 114L above the left diffusion 106. A gate structure 120, such as polysilicon, is disposed on the top oxide layer 116.
The following materials, processes and dimensions may be exemplary (note that the drawing is not “to scale”):
The substrate 102 may be a P-type silicon substrate, or a “P-well” (as illustrated) which is formed in an N-type or P-type silicon substrate.
The first and second diffusions 104 and 106 may both be doped N+, and either may serve as source (S) or drain (D), depending on operating conditions. Generally, the memory cell has left-right (as viewed) “mirror symmetry”.
The channel 108 may have a length (Leff, across the page, as viewed) of approximately 100 nm. (This dimension (Leff) depends on the “technology node”, currently 100 nm, which is becoming smaller and smaller).
The ONO stack 110 may have a length dimension (Ld, “length drawn”, across the page, as viewed) of approximately 120-150 nm, which is greater than the channel length (Leff). (This dimension (Ld) depends on the technology node.)
The channel 108 and the ONO stack 110 may both have a dimension, into the page (as viewed) of Wd (width drawn), typically slightly less than Leff, but may be slightly greater than Leff. This dimension generally depends on the process flow.
The bottom oxide layer 112 may comprise SiO2, formed by oxidation, and may have a thickness of from 3.0 to 6.0 nm, for example (but not limited to) 4.0 nm.
The storage nitride layer 114 may comprise Si3N4, deposited by a CVD, such as LPCVD, and may have a thickness of from 3.0 to 8.0 nm, for example (but not limited to). 4.0 nm.
The top oxide layer 116 may comprise SiO2, formed by nitride oxidation followed by oxide deposition, and may have a thickness of from 5.0 to 15.0 nm, for example (but not limited to) 10.0 nm.
The gate 120 may be doped N+.
Modes of NROM Operation
Voltages Vd and Vs, Vg and Vsub (or Vb) may be applied to each of the right and left diffusions 106 and 104, the gate 120 and the substrate 102, respectively, for operating the NROM cell. As will be noted, the left and right diffusions 104 and 106 may function as either source or drain, depending on the mode of operation.
For example to program the right bit 114R by channel hot electron (CHE) injection, the left diffusion 106 (acting as source, Vs) may be set to 0 volts (in an array, Vs may be set to between 0 volts and +0.7 volts),                the right diffusion 104 (acting as drain, Vd) may be set to +5 volts,        the gate 120 (Vg) may be set to +8-10 volts, and        the substrate 102 (Vb, Vsub) may be set to 0 volts        
And, to program the left bit 114L, Vs and Vd would be interchanged.
For example, to erase the right bit 114R, by hot hole injection (HHI),                the left diffusion 106 (acting as source, Vs) may be set to float (in an array, Vs may be set to between 0 volts and +4.5 volts),        the right diffusion 104 (acting as drain, Vd) may be set to +5 volts,        the gate (Vg) 120 may be set to −7 volts, and        the substrate 102 (V, Vsub) may be set to 0 volts.        
And, to erase the left bit 114L, Vs and Vd would be interchanged.
For example, to read the right bit 114R, using “reverse read”,                the right diffusion 104 (acting as source, Vs) is set to 0 volts        the left diffusion 106 (acting as drain, Vd) is set to +2 volts        the gate 120 (Vg) is set to +5 volts, and        the substrate 102 (Vb, Vsub) is set to 0 volts.        
And, to read the left bit 114L, Vs and Vd would be interchanged.
Commonly-owned US2007/0159880 and US 2007/0195607 disclose methods of operating NROM devices including programming and erasing, such as by Fowler Nordheim (−FN) electron tunneling from the top (gate), Hot Hole Injection (HHI) from the bottom (channel), Channel Hot Electron (CHE) injection from the bottom (channel), and Channel-Initiated Secondary Electron (CHISEL) injection from the bottom.
BE-SONOS
A structure which is similar to an NROM cell is a SONOS (silicon-oxide-nitride-oxide-silicon) cell, which also has an ONO stack disposed between the substrate and the gate structure (polysilicon).
FIG. 2A shows the structure of a BE (bandgap engineered) SONOS with ONO tunneling dielectric at the top, such as described in the article A Novel Gate-Injection Program/Erase P-Channel NAND-Type Flash Memory with High (10M Cycle Endurance), Hang-Ting Lue et al., Macronix International Co. Ltd., 2007 Symposium on VLSI Technology Digest of Papers, 978-4-900784-03-1, pp 140-141, incorporated in its entirety by reference herein.
Programming is performed by −FN electron injection from the poly gate (from the top). The device is erased by +FN hole injection, also from the poly gate (from the top). (“FN” is an abbreviation for Fowler-Nordheim.)
The following table lists typical device parameters for the gate-injection BE-SONOS device.
Tunneling Oxide (O3)1.3 nmInter Nitride (N2)2.1 nmInter Oxide (O2)1.7 nmTrapping Nitride (N1)8.0 nmBottom Oxide (O1)6.0 nm
FIG. 2B shows the structure of a BE (bandgap engineered) SONOS with ONO tunneling dielectric at the bottom, such as described in the article BE-SONOS: A Bandgap Engineered SONOS with Excellent Performance and Reliability, Hang-Ting Lue et al., Macronix International Co. Ltd., C) 2005, IEEE 0-7803-9269-8/05, incorporated in its entirety by reference herein.
For NOR, programming is performed by CHE (from the bottom) and is erased by −FN hole injection from the channel (from the bottom). For NAND programming is performed by +FN electron injection from the channel (from the bottom) and is erased by −FN hole injection from the channel (from the bottom)
The following table lists typical device parameters for the bottom-injection BE-SONOS device.
Blocking Oxide (O3)9.0 nmTrapping Nitride (N2)7.0 nmInter Oxide (O2) 1.8 nm*Inter Nitride (N1)2.0 nmBottom Oxide (O1)1.5 nm*The Inter Oxide (O2) may be 2.5 nm, see Reliability Model of Bandgap Engineered SONOS (BE-SONOS), Lue et al., MXIC IEDM, IEEE, 2006, incorporated in its entirety by reference herein.
Commonly-owned patents disclose structure and operation of NROM and related ONO memory cells. Some examples may be found in commonly-owned U.S. Pat. Nos. 5,768,192 and 6,011,725, 6,649,972 and 6,552,387.
Commonly-owned patents disclose architectural aspects of an NROM and related ONO array, (some of which have application to other types of NVM array) such as segmentation of the array to handle disruption in its operation, and symmetric architecture and non-symmetric architecture for specific products, as well as the use of NROM and other NVM array(s) related to a virtual ground array. Some examples may be found in commonly-owned U.S. Pat. Nos. 5,963,465, 6,285,574 and 6,633,496.
Commonly-owned patents also disclose additional aspects at the architecture level, including peripheral circuits that may be used to control an NROM array or the like. Some examples may be found in commonly-owned U.S. Pat. Nos. 6,233,180, and 6,448,750. See also commonly-owned U.S. Pat. No. 7,062,619.
Commonly-owned patents also disclose several methods of operation of NROM and similar arrays, such as algorithms related to programming, erasing, and/or reading such arrays. Some examples may be found in commonly-owned U.S. Pat. Nos. 6,215,148, 6,292,394 and 6,477,084.
Commonly-owned patents also disclose manufacturing processes, such as the process of forming a thin nitride layer that traps hot electrons as they are injected into the nitride layer. Some examples may be found in commonly-owned U.S. Pat. Nos. 5,966,603, 6,030,871, 6,133,095 and 6,583,007.
Commonly-owned patents also disclose algorithms and methods of operation for each segment or technological application, such as: fast programming methodologies in all flash memory segments, with particular focus on the data flash segment, smart programming algorithms in the code flash and EEPROM segments, and a single device containing a combination of data flash, code flash and/or EEPROM. Some examples may be found in commonly-owned U.S. Pat. Nos. 6,954,393 and 6,967,896.
Where applicable, descriptions involving NROM are intended specifically to include related oxide-nitride technologies, including SONOS (Silicon-Oxide-Nitride-Oxide-Silicon), MNOS (Metal-Nitride-Oxide-Silicon), MONOS (Metal-Oxide-Nitride-Oxide-Silicon), SANOS (Silicon-Aluminum Oxide-Nitride-Oxide-Silicon), MANOS (Metal-Aluminum Oxide-Nitride-Oxide-Silicon), and TANOS (Tantalum-Aluminum Oxide-Nitride-Oxide-Silicon), and the like used for NVM devices. Further description of NVM and related technologies may be found at “Non Volatile Memory Technology”, Vol. 1 & 2 (2005), Vol. 3 (2006) and Vol. 4 (2007), published by Saifun Semiconductor; “Microchip Fabrication”, by Peter Van Zant, 5th Edition 2004; “Application-Specific Integrated Circuits” by Michael John Sebastian Smith, 1997; “Semiconductor and Electronic Devices”, by Adir Bar-Lev, 2nd Edition, 1999; “Digital Integrated Circuits” by Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic, 2nd Edition, 2002 and materials presented at and through http://siliconnexus.com, “Design Considerations in Scaled SONOS Nonvolatile Memory Devices” found at: http://klabs.org/richcontent/MemoryContent/nvmt_symp/nvmts—2000/presentations/bu_white_s onos_lehigh_univ.pdf, “SONOS Nonvolatile Semiconductor Memories for Space and Military Applications” found at: http://klabs.org/richcontent/MemoryContent/nvmt_symp/nvmts—2000/papers/adams_d.pdf, “Philips Research—Technologies—Embedded Nonvolatile Memories” found at: http://www.research.philips.com/technologies/ics/nvmemories/index.html, and “Semiconductor Memory: Non-Volatile Memory (NVM)” found at: http://www.ece.nus.edu.sg/stfpage/elezhucx/myweb/NVM.pdf,
all of which are incorporated by reference herein in their entirety.